SSCAFBL=0, CSTRT=0, SSGTRGAF=0, SSELCB=0, SSCARBH=0, SSGTRGBF=0, SSCBRAH=0, SSCBRAL=0, SSELCD=0, SSCBFAL=0, SSGTRGBR=0, SSGTRGAR=0, SSELCC=0, SSCBFAH=0, SSCAFBH=0, SSCARBL=0, SSELCA=0
General PWM Timer Start Source Select Register
| SSGTRGAR | GTETRGA Pin Rising Input Source Counter Start Enable 0 (0): Counter start disabled on the rising edge of GTETRGA input 1 (1): Counter start enabled on the rising edge of GTETRGA input |
| SSGTRGAF | GTETRGA Pin Falling Input Source Counter Start Enable 0 (0): Counter start disabled on the falling edge of GTETRGA input 1 (1): Counter start enabled on the falling edge of GTETRGA input |
| SSGTRGBR | GTETRGB Pin Rising Input Source Counter Start Enable 0 (0): Counter start disabled on the rising edge of GTETRGB input 1 (1): Counter start enabled on the rising edge of GTETRGB input |
| SSGTRGBF | GTETRGB Pin Falling Input Source Counter Start Enable 0 (0): Counter start disabled on the falling edge of GTETRGB input 1 (1): Counter start enabled on the falling edge of GTETRGB input |
| SSCARBL | GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable 0 (0): Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 |
| SSCARBH | GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable 0 (0): Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 |
| SSCAFBL | GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable 0 (0): Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 |
| SSCAFBH | GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable 0 (0): Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 |
| SSCBRAL | GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable 0 (0): Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 |
| SSCBRAH | GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable 0 (0): Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 |
| SSCBFAL | GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable 0 (0): Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 |
| SSCBFAH | GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable 0 (0): Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 |
| SSELCA | ELC_GPTA Event Source Counter Start Enable 0 (0): Counter start disabled at the ELC_GPTA input 1 (1): Counter start enabled at the ELC_GPTA input |
| SSELCB | ELC_GPTB Event Source Counter Start Enable 0 (0): Counter start disabled at the ELC_GPTB input 1 (1): Counter start enabled at the ELC_GPTB input |
| SSELCC | ELC_GPTC Event Source Counter Start Enable 0 (0): Counter start disabled at the ELC_GPTC input 1 (1): Counter start enabled at the ELC_GPTC input |
| SSELCD | ELC_GPTD Event Source Counter Start Enable 0 (0): Counter start disabled at the ELC_GPTD input 1 (1): Counter start enabled at the ELC_GPTD input |
| CSTRT | Software Source Counter Start Enable 0 (0): Counter start disabled by the GTSTR register 1 (1): Counter start enabled by the GTSTR register |